1. Field of the Invention.
The present invention relates generally to digital computer systems, and more specifically to subsystems for interfacing host computer systems with serial communication lines.
2. Description of the Prior Art.
Communications between computers are extremely important to modern computer systems. Some computers have several independent serial communications ports which operate simultaneously. Controlling simultaneous communications sessions on several ports can place demands on a system processor which degrade overall system performance.
One solution to this performance problem is to use "smart" communications adapters. These adapters handle all of the low level details of a communications session. The adapters communicate with their host system to transfer data in relatively large blocks. Both received data and data to be transmitted are transferred between the adapter and the host system using block transfers. Direct memory access (DMA) can be used for such transfers to further reduce the processing burden placed on the host central processor.
In order to provide multiple communications ports in a system having a limited number of adapters, several ports can be placed on a single adapter. However, this approach can lead to significant problems. Data and command handling for several independent ports can become quite complex, especially at high communications rates. When different speeds and protocols are used on the different communications ports, the problem becomes greatly exacerbated. It becomes difficult for the adapter to insure that all communications ports are handled in a timely manner.
It would be desirable to provide a system suitable for use as a communications port adapter which can handled multiple independent ports without loss of data.